1. Field of the Invention
This invention relates generally between two communicating processes, and more particularly to a method and apparatus for line rate throughput for variable size packets being transmitted between microprocessors, while using single ported memories instead of dual ported memories.
2. Description of the Related Art
When multiple processors are in communication with each other, data must be transmitted between the processors. The data is written into memory/buffer by one processor and is read from the memory/buffer by another processor. The data stream consists of a number of packets and when communicating through the Internet, the packet sizes vary. Furthermore, depending on the protocol being used to transmit the data, each packet will have different headers that need to be stripped down by a receiving processor. FIG. 1 is a simplified schematic diagram of a host system configured to receive Ethernet packets. Host 100 includes software stack 102. Software stack 102 includes Internet Small computer System Interface (iSCSI) layer, Transmission Control Protocol (TCP) layer, Internet protocol security (IPSec) layer, and Internet protocol (IP) layer. As is generally known by those in the art, the software stack peels back the headers of a packet to receive the encapsulated data or builds up the packets for eventual transmission over network 108. Network interface card (NIC) 104 includes microprocessor 106 configured to receive and transmit Ethernet packets over network 108.
One of the shortcomings of the design illustrated in FIG. 1 is that a single host processor is responsible for performing the operations associated with software stack 102. Thus, as throughputs are continually being pushed higher, the single processor of the host is limited in the capability of supporting the throughput of the incoming data stream because of the built in latencies associated with the single processor of a host system. That is, the processor of the host can not consistently provide the incoming data to other processors in a manner which limits latencies and at least supports the throughput of an incoming data stream.
FIG. 2 is a schematic diagram illustrating a producer/consumer relationship between two processors. Processor 1110 is a producer, i.e., processor 1 writes data to single ported memory 112 to be used by processor 2114. Processor 2114 is a consumer, i.e., processor 2 reads data 446 from single ported memory 112. Processor 1110 produces messages which may be configured as a byte or a burst of bytes. Where one processor is talking to another processor, the manner in which data is written into and read from single ported memory 112 impacts the throughput of the system. For example, where a first in-first out (FIFO) method is employed, the producer writes a message into single ported memory 112 and once the message has been completely written into the memory, the consumer reads the message. One skilled in the art will appreciate that the FIFO method can write a single word as a message, i.e., word FIFO, or a contiguous set of words as a message, i.e., message FIFO.
However, the throughput of the producer/consumer relationship must be configured to sustain the line rate. That is, the consumer must be allowed to consume at its maximum line rate so as not to be waiting. One implementation currently being employed to ensure the consumer is operating at its line rate, uses a dual port memory. Dual port memories allow for a consumer to read from memory while a producer is writing to memory, as opposed to a single ported memory, which does not allow for the simultaneous reading and writing from memory. Shortcomings of the dual ported memories include the fact that the dual ported memories are twice as large as single ported memories and as such, take up valuable surface area on a semiconductor chip and consume more power. Additionally, the cost for dual ported memories is expensive relative to single ported memories.
Another implementation being employed to ensure the consumer runs at its line rate, uses two single ported memories, also referred to as ping-pong memories. Here, one memory may be written into while another memory is read from. While the ping-pong memories improve throughput, especially where the packets are all the same size, the ping-pong memories are not able to keep the consumer running at a rate sufficient to maintain an incoming line rate when the packet size of the data packets varies.
In view of the foregoing, there is a need to maintain an incoming line rate for processors in communication with each other when the data being exchanged includes variable packet sizes.